The present invention relates to a semiconductor package, and more particularly to a stack package, which employs a pattern die having redistribution parts.
As is generally known in the art, the semiconductor packaging technology has been focused on ways to mount more number of packages on a limited-size substrate and thereby to decrease the relative size of a package. A chip size package and a ball grid array (BGA) package are typical examples.
In addition to reducing size, the recent trend in the packaging technology is directed to achieving the desired high capacity by packaging at least two or more semiconductor chips into a single package. For example, vigorous studies are being made for development of a stack package and a multi-chip package (MCP) in which a plurality of semiconductor chips are vertically or horizontally placed on a substrate.
However, these types of conventional stack packages and the MCPs utilize bonding wires to electrically connect a plurality of semiconductor chips that are vertically stacked. As a consequence, the thickness of the entire package becomes undesirably thick, and the reliability and the yield of the package are adversely influenced by the bonding wire sweep and shorts in a molding process. Further, as the length of the bonding wire increases, the electrical characteristics of the package are likely to be deteriorated. In order to overcome these problems, a technique for manufacturing an MCP using some form of redistribution layers has been disclosed in Korean Patent Application No. 10-2003-0087282.
FIG. 1 is a cross-sectional view of the MCP disclosed in the above patent reference. Two pairs of semiconductor chips 2a, 2b and 2c, 2d each chip having redistribution layers (not shown) are attached to the upper and lower surfaces, respectively, of a die paddle 3. The redistribution layers for each of the semiconductor chips 2a, 2b, 2c, 2d are electrically connected to inner leads 4 by bonding wires 6 and to the other chip on the same surface of the die paddle 3 by bonding wires 7. The semiconductor chips 2a, 2b, 2c, 2d, the die paddle 3, the inner leads 4, and the bonding wires 6, 7 are encapsulated by a molding material 8. The reference numeral 5 designates outer leads.
Since the MCP is constructed using semiconductor chips having redistribution layers, the overall thickness of the package can be decreased when compared to the conventional art, and the problem caused due to sweeping of bonding wires can be substantially solved. Also, as the length of the bonding wire decreases, the electrical characteristics of the package can be improved when compared to the conventional art.
Nevertheless, in the MCP as described above, since the redistribution layers must be formed on the semiconductor chips which are actually driven and at least two-layered redistribution structure must be formed, it is difficult to form the redistribution layers.
Moreover, in another type of MCP different from the MCP described above, even though redistribution layers are formed, when it is required to form a stack of chips only through wire bonding, it may be necessary to connect oppositely positioned bonding pads. If the oppositely positioned bonding pads are connected to one another using elongated bonding wires 23 and 24 as shown in FIG. 2 or using a separate substrate (not shown), the process margin may decrease. Therefore, a stable electrical connection cannot be formed only through forming of redistribution layers. In FIG. 2, the reference numerals 20, 22 designate semiconductor chips, and the reference numeral 21 is an adhesive.
Further, in case of forming electrical connections using redistribution layers, the electrical connections in the same direction do not cause any problem. However, when interconnecting the oppositely positioned bonding pads, since the two-layered redistributions should be used, it is actually difficult to use the redistributions.